1. Field of the Invention
The present invention relates to a technology of supporting logic verification of a circuit.
2. Description of the Related Art
In the design of large scale integration (LSI) circuits, logic verification to verify whether the LSI circuit operates correctly is essential. Particularly since larger-scale, higher-performance, faster speed, and lower-power consumption are demanded of LSI circuits, logic verification is important to maintain high quality. On the other hand, improved work efficiency by a reduction in the design period is demanded.
Generally, tests for logic verification of LSI circuits include a test to confirm operations for normal events (normal-event operations) and a test to confirm operations for abnormal events (abnormal-event operations). In the former (normal-event test), fundamental operations of the LSI circuit are confirmed using normal scenarios that implement LSI function. In the latter (abnormal-event test), abnormal-event operations of the LSI circuit are confirmed using exception scenarios that implement exception handling of the LSI.
Recently, various techniques of enhancing verification efficiency have been disclosed. For example, a technique is disclosed in which specification description and register transfer level (RTL) are correlated from a specification description of behavior level concerning a verification subject circuit and a description of the RTL corresponding to the specification description, and RTL test sequence data is generated based on a test sequence to verify the specification description (see, for example, Japanese Patent Application Laid-open Publication No. H07-254008).
According to the technique, an RTL test sequence derived from description modification and an expected value sequence are automatically generated, reducing the time required for test sequence generation that has been generated manually.
However, the abnormal-event test is not considered in the conventional technique disclosed in Japanese Patent Application Laid-open Publication No. H07-254008. In LSI logic verification, bugs typically occur more often in the abnormal-event test than in the normal-event test as fundamental LSI circuit operations confirmed in the normal-event test cause few bugs. Meanwhile, as units, ports, and combinations thereof subject to verification in the abnormal-event test are numerous, it is difficult to judge to what extent the operations should be verified, and unexpected bugs are likely to occur.
As a result, a verification engineer must verify the abnormal-event operations by trial and error, causing increased load on the verification engineer and prolonging the period required for verification.